View DS2167_529321.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DS2167/DS2168
DS2167/DS2168 ADPCM Processor
FEATURES
PIN ASSIGNMENT
RST TM0 TM1 A0 A1 A2 A3 A4 A5 SPS MCLK VSS 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VDD YIN CLKY FSY YOUT CS SDI SCLK XOUT FSX CLKX XIN
* Speech compression chip compatible with standard
ADPCM algorithms: - DS2167 supports "new" T1Y1 recommendations (July 1986) and "new" CCITT G.721 recommendations - DS2168 supports "old" CCITT G.721 recommendations
* Dual independent channel architecture - device may
be programmed to perform full duplex, 2-channel expansions, or 2-channel compressions
* Interconnects directly with -law or A-law codec/filter
devices
24-Pin DIP (600 MIL) CLKY FSY YOUT CS SDI SCLK XOUT NC TM1 TM0 RST NC VDD YIN NC A0 A1 A2 A3 A4 A5 54 3 2 6 7 8 9 28-Pin PLCC
* Serial PCM and control port interfaces minimize "glue
logic" in multiple channel applications - On-chip channel counters identify input and output timeslots in TDM-based systems - Unique addressing scheme simplifies device control; 3-wire port shared among 64 devices - Bypass and idle features allow dynamic allocation of channel bandwidth, minimize system power requirements
1 28 27 26 25 24 23 22
21 10 20 11 12 13 14 15 16 17 1819 SPS MCLK VSS NC XIN CLKX FSX
* Hardware mode intended for stand-alone use
- No host processor required - Ideal for voice mail applications
* 28-pin surface-mount package available, designated
DS2167Q/DS2168Q
DESCRIPTION
The DS2167 and DS2168 are dedicated digital signal processor (DSP) CMOS chips optimized for Adaptive Differential Pulse Code Modulation (ADPCM) based compression algorithms. The devices halve the transmission bandwidth of "toll quality" voice from 64K to 32K bits/second and are utilized in PCM-based telephony networks.
022698 1/15
DS2167/DS2168
PRODUCT OVERVIEW
The DS2167 and DS2168 contain three major functional blocks: a high performance (10 MIPS) DSP "engine," two independent PCM data interfaces ("X" and "Y") which connect directly to serial time division multiplexed (TDM) backplanes and a microcontroller-compatible serial port for on-the-fly device configuration. A 10MHz master clock is required by the DSP engine. The devices' dual channel architecture supports full duplex, dual compression or dual expansion operation. The PCM data interfaces support 1.544, 2.048 and 4.096 MHz data rates. Each device samples the serial PCM or ADPCM bit stream during a user-programmed input timeslot, processes the data and outputs the result during a user-programmed output timeslot.
Each PCM interface has a control register which specifies functional characteristics (compress, expand, bypass and idle), data format (-law or A-law) and algorithm reset control. With the SPS pin strapped high, the software mode is enabled and the serial port is used to program control and timeslot registers. In this mode, a novel addressing scheme allows multiple devices to share a common 3-wire control bus, simplifying system level interconnect. With SPS low, the hardware mode is enabled. This mode disables the serial port and maps appropriate control register bits to address and port inputs. Under hardware mode, no host controller is required and all PCM I/O defaults to timeslot 0. This stand-alone mode is compatible with popular codecs.
DS2168 BLOCK DIAGRAM Figure 1
FSX CLKX XIN XOUT "X" SIDE PCM/ADPCM DATA INTERFACE
SCLK SPS CS SDI A0 - A5 SERIAL PORT CONTROL/ HARDWARE MODE LOGIC ADPCM PROCESSING "ENGINE"
MCLK
RST TM0 TM1 RESET AND TEST LOGIC VDD VSS
FSY CLKY YIN
"Y" SIDE PCM/ADPCM DATA INTERFACE YOUT
022698 2/15
DS2167/DS2168
PIN DESCRIPTION Table 1
PIN 1 SYMBOL RST TYPE I DESCRIPTION Reset. A high-low-high transition clears all internal registers and reset both algorithms. The device should be reset on system power-up, and/or when changing to/from hardware mode. Test Modes 0 and 1. Tie to VSS for normal operation Address Select. A0=LSB; A5=MSB. Must match address/command word to enable serial port write.
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
TM0 TM1 A0 A1 A2 A3 A4 A5 SPS MCLK VSS XIN CLKX FSX XOUT SCLK SDI CS YOUT FSY CLKY YIN VDD
I
I
I I - I I I O I I I O I I I -
Serial Port Select. Tie to VDD to select the serial port, to VSS to select the hardware mode. Master Clock. 10 MHz clock for ADPCM processing "engine"; may asynchronous to SCLK, CLKX and CLKY. Signal Ground. 0.0 volts X Data In. Samples on falling edge of CLKX during selected timeslots. X Data Clock. Data clock for X side PCM interface; must be coherent and rising edge aligned with FSX. X Frame Sync. 8 KHz frame sync for X side PCM interface. X Data Out. Updated on rising edge of CLKX during selected timeslots. Serial Data Clock. Used to write serial port registers. Serial Data In. Data for onboard control registers. Sampled on rising edge of SCLK. Chip Select. Must be low to write the serial port. Y Data Out. Updated on rising edge of CLKY during selected timeslots. Y Frame Sync. 8 KHz frame sync for Y side PCM interface. Y Data Clock. Data clock for Y side PCM interface; must be coherent and rising edge aligned with FSY. Y Data In. Samples on falling edge of CLKY during selected timeslots. Positive Supply. 5.0 volts.
HARDWARE RESET
RST allows the user to reset both channel algorithms and register contents. This input must be held low for at least 1 ms on system power-up after master clock is stable to assure proper initialization of the device. RST
should also be asserted when changing to/from the hardware mode. RST clears all bits of the control register except IPD; IPD is set for both channels, powering down the device.
022698 3/15
DS2167/DS2168
HARDWARE MODE
The hardware mode is intended for preliminary system prototyping or for applications which do not require the features of the serial port. Tying SPS to VSS disables the serial port, clears all internal registers and maps IPD, /A and CP/EX of the X and Y side interfaces to the
port and address inputs. Input and output timeslots for the X and Y side interfaces are fixed at 0. Such applications include, but are not limited to: 1) systems in which timeslot and algorithm are fixed, 2) stand-alone ADPCM combo applications, 3) "hardware" oriented systems where no host controller is available.
HARDWARE MODE Table 2
PIN #/NAME 4/A0 REG. LOCATION CP/EX (X) NAMES AND DESCRIPTION Channel X coding 0 = Expand 1 = Compress 6/A2 /A (X) Channel X data format 0 = A-law 1 = -law 7/A3 CP/EX (Y) Channel Y coding 0 = Expand 1 = Compress 9/A5 /A (Y).2 Channel Y data format 0 = A-law 1 = -law 18/SDI IPD (Y) Y idle select 0 = Channel active 1 = Channel idle 19/CS IPD (X) X idle select 0 = Channel active 1 = Channel idle
NOTES:
1. SCLK, A1 and A4 must be tied to VSS when the hardware mode is selected. 2. When both X and Y sides are idled, the devices enter a stand-by mode which significantly reduces power consumption. 3. The DS2167 will power-up within 200 ms after the X or Y side is reactivated (SDI and/or CS not equal to 0) from standby. 4. The DS2168 must be hardware reset when reactivated from standby. Power-up occurs immediately after the reset.
022698 4/15
DS2167/DS2168
CODEC/FILTER HARDWARE MODE INTERCONNECT Figure 2
POWER ON RESET (DS1231)
TRANSMIT FRAME SYNC TRANSMIT DATA CLOCK
RST VCC -5.0 V VBB CODEC/FILTER GNDA MCLKX DX FSX BCLKX DR FSR BCLK/ CLKSEL MCLK/PDN VFRO SCLK XIN FSX DS2167/DS2167 CLKX YOUT FSY CLKY
VDD A0 TP3054 (-LAW) A5 A2 XOUT YIN A3 A4 A1 TRANSMIT DATA RECEIVE DATA TP3057 (-LAW)
TSX TRANSMIT ANALOG INTERFACE VFXI+ VFSIGSX RECEIVE ANALOG INTERFACE
SPS POWER DOWN TM0 TM1 VSS SDI CS MCLK 10 MHz CLOCK ACTIVE
RECEIVE DATA CLOCK RECEIVE FRAME SYNC
NOTE:
Suggested Codec/Filters TP305X National Semiconductor ETC505X SGS-Thomson Microelectronics MC1455XX Motorola TCM29CXX Texas Instruments HD44238C Hitachi *other generic Codec/Filter devices can be substituted.
SOFTWARE MODE
Tying SPS high enabled the software mode. In this mode, a host microcontroller writes configuration data to the DS2167/DS2168 serial port via inputs SCLK, SDI, and CS. Independent control and timeslot registers establish operating characteristics for the X-side and Yside PCM interfaces.
A0-A5. If no match occurs, the device ignores the following configuration data. If an address match occurs, the next three bytes written are accepted as control, input and output timeslot data. Bit ACB.6 determines which side (X or Y) of the device is to be updated.
CONTROL REGISTER
The control register establishes idle, algorithm reset, bypass, data format and channel coding for the selected PCM interface. The X and Y side PCM interfaces may be independently disabled (output tri-stated) via IPD; when IPD is set for
ADDRESS/COMMAND BYTE
In the software mode, the address/command byte is the first byte written to the serial port; it identifies which of 64 possible ADPCM processors sharing the port wiring is to be updated. Address data must match that at inputs
022698 5/15
DS2167/DS2168
both X and Y interfaces, the device enters a low-power standby mode. The DS2167 will power-up within 200 ms after the X or Y side is reactivated (IPD=0) from standby. The DS2168 requires an external hardware reset after IPD is cleared to "wake-up" from standby. The DS2168 will power-up immediately after the low-high transition on RST. ALRST resets the algorithm coefficients for the selected channel to their initial values. ALRST will be cleared by the device when the algorithm reset is complete. The bypass feature is enabled when BYP is set and IPD is clear. During bypass, no expansion or compression of data occurs. This feature allows the user to interchange timeslots under control of the timeslot registers. Bypass
operates on byte-wide slots when CP/EX=1, on nibblewide slots when CP/EX=0. A-law (/A=0) or -law PCM (/A=1) coding is independently selected for the X and Y side interfaces by bit /A. If BYP and IPD are clear, CP/EX determines if input data is to be compressed or expanded.
TIMESLOT ASSIGNMENT
On-chip counters establish when PCM data I/O occurs and are programmed via the timeslot registers. Timeslot size (4 or 8 bits wide) is determined by the state of CP/EX. Timeslots are counted from the rising edge of FSX and FSY.
ADDRESS/COMMAND BYTE Figure 3
(MSB) - SYMBOL - X/Y X/Y POSITION ACB.7 ACB.6 A5 A4 A3 A2 A1 (LSB) a0
NAME AND DESCRIPTION Reserved, must be 0 for proper operation. X/Y Channel Select. 0 = Update channel Y characteristics. 1 = Update channel X characteristics. MSB of Device Address.
A5 A4 A3 A2 A1 A0
ACB.5 ACB.4 ACB.3 ACB.2 ACB.1 ACB.0
LSB of Device Address.
022698 6/15
DS2167/DS2168
CONTROL REGISTER Figure 4
(MSB) - SYMBOL - - IPD - POSITION CR.7 CR.6 CR.5 IPD ALRST BYP /A - (LSB) CP/EX
NAME AND DESCRIPTION Reserved, must be 0 for proper operation. Reserved, must be 0 for proper operation. Idle and Power Down. 0 = channel enabled. 1 = channel disabled (output tri-stated). Algorithm Reset. 0 = Normal operation. 1 = Reset algorithm for selected channel. Bypass. 0 = Normal operation. 1 = Bypass selected channel. Data Format 0 = A-law. 1 = -law. Reserved, must be 0 for proper operation. Channel Coding. 0 = Expand (decode) selected channel. 1 = Compress (encode) selected channel.
ALRST
CR.4
BYP
CR.3
/A
CR.2
- CP/EX
CR.1 CR.0
INPUT TIMESLOT REGISTER Figure 5
(MSB) - SYMBOL - - D5 D4 D3 D2 D1 D0 - POSITION ITR.7 ITR.6 ITR.5 ITR.4 ITR.3 ITR.2 ITR.1 ITR.0 LSB of input timeslot word. D5 D4 D3 D2 D1 (LSB) D0
NAME AND DESCRIPTION Reserved, must be 0 for proper operation. Reserved, must be 0 for proper operation. MSB of input timeslot word.
022698 7/15
DS2167/DS2168
OUTPUT TIMESLOT REGISTER Figure 6
(MSB) - SYMBOL - - D5 D4 D3 D2 D1 D0 - POSITION OTR.7 OTR.6 OTR.5 OTR.4 OTR.3 OTR.2 OTR.1 OTR.0 LSB of output timeslot word. D5 D4 D3 D2 D1 (LSB) D0
NAME AND DESCRIPTION Reserved, must be 0 for proper operation. Reserved, must be 0 for proper operation. MSB of output timeslot word.
PCM I/O TIMING (1.544 MHz BACKPLANE) Figure 7
CLKX, CLKY 193 FSX, FSY XIN, YIN MSB XOUT, YOUT LSB TIMESLOT 0 TIMESLOT N TIMESLOT 23 193
ADPCM I/O TIMING (1.544 MHz BACKPLANE) Figure 8
CLKX, CLKY 193 FSX, FSY XIN, YIN MSB XOUT, YOUT LSB TIMESLOT 0 TIMESLOT 1 TIMESLOT N TIMESLOT 45 TIMESLOT 46 TIMESLOT 47 193
022698 8/15
DS2167/DS2168
SERIAL PORT WRITE
All port writes are initiated by driving CS low and terminated when CS returns high. Data is sampled on the rising edge of SCLK and must be written to the device LSB first. Writes to the device may be two bytes (address/
command and control) or four bytes (address/command, control, input timeslot and output timeslot) in length. Writes should be terminated on byte boundaries to insure data integrity. PCM and ADPCM outputs will tristate during register updates.
SERIAL PORT WRITE Figure 9
CS
SCLK
SDI1
A0
A1
A2
A3
A4
A5
X/Y
-
CR0 CR1 CR2 CR3 CR4
A0
A1
NOTE:
1. 2-byte write shown.
8051-BASED CONTROL SYSTEM Figure 10
8051 CONTROLLER P1.0 RXD TXD POWER-ON RESET (DS1231)
RST TM0 TM1 A0 DS2167/68 #0 A1 A2 A3 A4 A5 SPS MCLK VSS
VDD YIN CLKY FSY YOUT CS SDI SCLK XOUT FSX CLKX XIN
RST TM0 TM1 A0 A1 A2 A3 A4 A5 SPS MCLK VSS DS2167/68 #1
VDD YIN CLKY FSY YOUT CS SDI SCLK XOUT FSX CLKX XIN
RST TM0 TM1 A0 A1 A2 A3 A4 A5 SPS MCLK VSS DS2167/68 #63
VDD YIN CLKY FSY YOUT CS SDI SCLK XOUT FSX CLKX XIN
10 MHz CLOCK
PCM DATA HI-WAY "Y"
PCM DATA HI-WAY "X"
EEEE E EEEE E
A2
022698 9/15
DS2167/DS2168
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature -1.0V to 7.0V 0C to +70C -55C to 125C 260C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER Logic 1 Logic 0 Supply SYMBOL VIH VIL VDD MIN 2.0 -0.3 4.5 TYP MAX VCC +0.3 +0.8 5.5 UNITS V V V
(0C to 70C)
NOTES
CAPACITANCE
PARAMETER Input Capacitance Output Capacitance SYMBOL CIN COUT MIN TYP MAX 5 10 UNITS pF pF
(tA = 25C)
NOTES
DC ELECTRICAL CHARACTERISTICS
PARAMETER Supply Current (Active) Supply Current (Idle) Input Leakage Output Leakage Output Current @ 2.4V Output Current @ 0.4V SYMBOL IDDA IDDPD IIL ITRI IOH IOL -1.0 -1.0 -1.0 4.0 MIN TYP 30 1
(0C to 70C; VDD = 5V + 10%)
MAX UNITS mA mA +1.0 +1.0 A A mA mA 4 NOTES 1,2 1,2,3
NOTES:
1. CLKX = CLKY = 1.544 MHz; MCLK = 10 MHz. 2. Outputs open; inputs swinging full supply levels. 3. Both channels in idle mode. 4. XOUT and YOUT when tri-stated.
022698 10/15
DS2167/DS2168
PCM INTERFACE AC ELECTRICAL CHARACTERISTICS
PARAMETER MCLK Period MCLK Pulse Width MCLK Rise and Fall Times CLKX, CLKY Period CLKX, CLKY Pulse Width CLKX, CLKY Rise and Fall Times Hold Time from CLKX, CLKY to FSX, FSY Setup Time from FSX, FSY to CLKX, CLKY low Hold Time from CLKX, CLKY low to FSX, FSY low XIN, YIN Setup to CLKX, CLKY low XIN, YIN Hold to CLKX, CLKY low Delay Time from CLKX, CLKY to Valid XOUT, YOUT Delay Time from CLKX, CLKY to XOUT, YOUT Tri-stated SYMBOL tPM tWMH, tWML tRM, tFM tPXY tWXYH, tWXYL tRXY, tFXY tHOLD tSF tHF tSD tHD tDXYO tDXYZ 0 50 100 50 50 10 20 244 100 45 MIN TYP 100 50 5 488 244 10
(0C to 70C, VDD = 5V + 10%)
MAX UNITS ns 55 10 5208 ns ns ns ns 20 ns ns ns ns ns ns 150 150 ns ns 1 1 1 1 1 2 1,2,3 4 NOTES 5
NOTES:
1. Measured at VIH = 2.0V, VIL = 0.8V, and 10 ns maximum rise and fall times. 2. Load = 150 pF + 2 LSTTL loads. 3. For LSB of PCM byte or ADPCM nibble. 4. Maximum width of FSX, FSY is one CLKX, CLKY period. 5. MCLK = 10 MHz + 500 ppm.
022698 11/15
DS2167/DS2168
MASTER CLOCK/RESET AC ELECTRICAL CHARACTERISTICS
PARAMETER MCLK Period MCLK Pulse Width RST Pulse Width SYMBOL tPM tWMH, tWML tWRL 45 1 MIN TYP 100 50
(0 to 70C, VDD = 5V + 10%)
MAX UNITS ns 55 ns ms NOTES 5
SERIAL PORT AC ELECTRICAL CHARACTERISTICS
PARAMETER SDI to SCLK Setup SCLK to SDI Hold SCLK Low Time SCLK High Time SCLK Rise and Fall Times CS to SCLK Setup SCLK to CS Hold CS Inactive Time SCLK Setup to CS Falling SYMBOL tDC tCDH tCL tCH tR, tF tCC tCCH tCWH tSCC 50 250 250 50 MIN 55 55 250 250 TYP
(0C to 70C, VDD = 5V + 10%)
MAX UNITS ns ns ns ns 100 ns ns ns ns ns NOTES 1 1 1 1 1 1 1 1 1
NOTES:
1. Measured at VIH = 2.0V, VIL = 0.8V, and 10 ns maximum rise and fall times. 2. MCLK = 10 MHz + 500 ppm.
022698 12/15
DS2167/DS2168
PCM INTERFACE AC TIMING DIAGRAM Figure 11
tPXY tHOLD CLKX CLKY tHF FSX FSY tSF tSD tHD tRXY tFXY tWXYH tWXYL
XOUT YOUT
MASTER CLOCK/RESET AC TIMING DIAGRAM Figure 12
tPM tRM tFM tWMH tWML
MCLK tWRL RST
SERIAL PORT WRITE AC TIMING DIAGRAM Figure 13
tCWH CS
SCLK tCL
SDI
tCDH
EEEEEE EEEEEE
EEEE EEEE EEEEE EEEE EEEE EEEEE
EEEEEEEEE EEEEEEEEE
tDXYO tDXYZ tCC tSCC tCH tR tF tCCH tDC
022698 13/15
XIN YIN
DS2167/DS2168
DS2167/DS2168 ADPCM PROCESSOR 24-PIN DIP
B
D
1 A
E
C J
F
K
G
H
INCHES DIM A IN. MM B IN. MM C IN. MM D IN. MM E IN. MM F IN. MM G IN. MM H IN. MM J IN. MM K IN. MM MIN 1.245 31.62 0.530 13.46 0.140 3.56 0.600 15.24 0.015 0.380 0.120 3.05 0.090 2.29 0.625 15.88 0.008 0.20 0.015 0.38 MAX 1.270 32.25 0.550 13.97 0.160 4.06 0.625 15.88 0.050 1.27 0.145 3.68 0.110 2.79 0.675 17.15 0.012 0.30 0.022 0.56
022698 14/15
DS2167/DS2168
DS2167/DS2168Q ADPCM PROCESSOR 28-PIN PLCC
E E1 B L1 N 1
D1
D
D2
B1 CH1 e1
C
A
E2 A2 INCHES DIM. A A1 A2 B B1 C D D1 D2 E E1 E2 L1 N e1 CH1 MIN. 0.165 0.090 0.020 0.026 0.013 0.009 0.485 0.450 0.390 0.485 0.450 0.390 0.060 28 0.050 BSC 0.042 0.048 MAX. 0.180 0.120 - 0.033 0.021 0.012 0.495 0.456 0.430 0.495 0.456 0.430 - - A1
022698 15/15

▲Up To Search▲

Price & Availability of DS2167

	To Download DS2167 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .